The present invention relates to data latch timing adjustment apparatus for adjusting the timing of latching data which has been output from semiconductor circuits such as memories or LSIs.
The timing of reading out data from a memory is generally determined in designing the memory, so that the timing of reading out data changes depending on the position and characteristics of the memory and the influence of ambient temperatures, for example. Accordingly, if the readout data is latched at a fixed latch timing, the data is latched erroneously. In order to adjust the latch timing of the readout data, a DIP switch, for example, is conventionally provided to normally latch the output data from the memory.
However, this method has a drawback of requiring additional processes for this adjustment. In view of this, a timing adjustment circuit for automatically adjusting latch timing of data read out from a memory was proposed in, for example, Japanese Laid-Open Publication No. 2001-350668.
FIG. 16 is the block diagram showing a timing adjustment circuit disclosed in the publication. FIG. 16 shows a circuit for adjusting latch timing of data read out from a memory a, and in this circuit, a write control section b writes given data into the memory a at an address predetermined for checks. In this case, the data written at the address by the write control section b is stored in a write data storing section c.
A read control section d outputs a timing signal to the memory a to cause the data written into the memory a at the address to be read out and also outputs, to a latch pulse delaying section e, latch pulse signals for latching the data read out from the memory a using the timing signal. The latch pulse delaying section e includes (n+1) delay circuits e0 through en and delays the latch pulse signals from the read control section d by different amounts of time, thereby generating and outputting a plurality of delayed pulse signals. Each of (n+1) latch circuits f0 through fn receives the readout data from the memory a and an associated one of the latch pulse signals and n delayed pulse signals output from the latch pulse delaying section e, and latches the readout data from the memory a using the received pulse signal. Each of (n+1) comparison circuits g0 through gn compares the latched data from an associated one of the latch circuits f0 through fn with an associated one of the data pieces stored in the write data storing section c. A determination section h determines an optimum pulse signal for the latch timing of the readout data from the memory a from among the latch pulse signals and the delayed pulse signals from the latch pulse delaying section e based on results of comparison at the comparison circuits g0 through gn. A selection part i selects an output of one of the (n+1) latch circuits f0 through fn which has received the optimum latch timing, based on a result of determination at the determination section h.
In this manner, an optimum latch timing for the readout data from the memory a is determined and adjusted automatically, in the above publication.
If the operation speed of a memory further increases, data is also read out from the memory at higher speed and the time required for determining the readout data from the memory is shortened accordingly. Therefore, to normally latch the readout data from the memory, a detailed adjustment is needed.
However, in order to perform a detailed delay adjustment or enlarge the adjustable range, the technique disclosed in the publication needs a large number of delay circuits with small delays so that the latch pulse delaying section e generates a large number of delayed pulse signals with minute delay differences. As a result, the technique disclosed in the publication has a drawback of requiring a large number of latch circuits and comparison circuits associated with the large number of delayed pulse signals. This drawback is found not only in latch timing of the readout data from the memory but also in latch timing of data read out from LSIs in the same manner.